This application is a continuation in part of, NTC 94042, application Ser. No. 11/141,656, filed May 31, 2005, entitled “method for forming a semiconductor device.”
The present invention relates in general to a method for forming a semiconductor device, and more particularly to a method for forming word lines of a semiconductor device.
Semiconductor devices, such as memory devices, Dynamic Random Access Memory (DRAM) for storage of information, or others, are currently in widespread use, in a myriad of applications.
The conventional method of forming transistor and bit line contact, however, requires at least two photolithography processes resulting in higher fabrication costs relative to a mask or reticle. Serious misalignment among the four photolithography processes, consisting of the capacitor, active area, transistor, and bit line contact, also occurs to affecting fabrication field. The determined width of the word line occupies the space for the bit line contact. Thus, shorts between bit line contact and word line are easily inducted causing contact fail. Particularly, the failures may become increasingly serious with shrinkage of DRAM dimensions. Accordingly, a new method for forming word and bit line contacts of a memory device is desirable.